This invention relates to a semiconductor device having a semiconductor elements such as a DRAM memory cell and a manufacturing method thereof, and particularly relates to a countermeasure for preventing a capacity storage electrode contact, a bit line contact and the like from increase in contact resistance.
In these days, high-density semiconductor devices are required, so that a semiconductor element provided thereto are being miniaturized. Therefore, the dimensions of a contact member which connects the semiconductor element to a wiring and of the overlap portion of the contact member and the element is being minimized.
Referring to accompanying drawings, a conventional semiconductor device is explained below. FIG. 14(a) is a plan view showing a DRAM memory cell array using a conventional stack type capacitor cell. FIG. 14(b) shows a part of FIG. 14(a) in enlarged scale. FIG.15 is a section, taken along the line XV--XV in FIG. 14(a). As shown in FIG. 14(a) and FIG. 15, a surface region of a P-type semiconductor substrate 1 is defined to a plurality of active regions Rac by an isolations 4. A switching transistor 8 composing the DRAM memory cell is formed at each active region Rac. Formed at each switching transistor 8 are two impurity doped diffusion regions, i.e. a drain region 2 and a source region 3. A gate electrode 7 for controlling channel current is provided, through a gate oxide layer 6, between the drain and the source of each switching transistor, i.e. above a channel region. A word line 5 which connects the gate electrodes 7 of the respective switching transistors is formed over the isolation 4 and the active region Rac. The word line 5 is linearly formed so as to connect adjacent switching transistors in a lateral direction of the plan view of FIG. 14(a).
In the section of FIG.15, the word line 5 is indicated as a word line on the isolation 4 and as a gate electrode 7 on the active region Rac for convenience sake. Upper and side parts of each electrode 7 are covered with a first insulating layer 9 composed of side walls 9a and upper protection layer 9b, in the form of LDD structure. Accordingly, the drain region 2 and the source region 3 have respectively a heavily doped region and a lightly doped region. Formed on the drain region 2 is a second insulating layer 12 which is patterned after deposition on the entire surface of the memory cell array part. As shown in enlarged scale in FIG. 14(b), a part of the second insulating layer 12 is removed which corresponds to the source region 3 of each switching transistor. In detail, as shown in the section of FIG.15, the second insulating layer 12 is removed at a region including an overhead region on a part of the source region 3, excepting a part adjacent to the isolation 4, and an overhead region on the first insulating layer 9 therearound. Hereinafter the region is referred to as removed region Ret. A capacity storage electrode 13 is formed on the second insulating layer 12. A capacity insulating layer 14 covers the capacity storage electrode 13, and a plate electrode 15 is formed on the capacity insulating layer 14. As shown in FIG. 14(b), a dotted region indicates a region at which a capacity storage electrode contact 11 for connecting the capacity storage electrode 13 and the source region 3 is to be formed. In general, a play 16 is provided between the capacity storage electrode contact 11 and the source region 3, taking consideration of displacement of photo-masks.
FIG.16 explains the displacement at a photo-lithography process, wherein a locational displacement arises between a mask for forming each part of the switching transistor 8 and a mask for patterning the second insulating layer 12 at the part corresponding to that in FIG. 14(b). The play 16 between an extreme end of the removed region Ret and an extreme end of the source region 3 is extremely small, 0.05 .mu.m, and it is difficult to form the removed region Ret at the accurate position according to alignment accuracy of the patterning in the photo-lithography technique in the present time. As a result, the removed region Ret may be shifted upward or downward over the play 16 as shown in FIG.16. In addition to the mask displacement, because of the micro dimension of the removed region Ret (e.g., 1.1 .mu.m.times.0.5 .mu.m), resolution at the photo-lithography process is so insufficient as to cause a tailing of resist pattern with a result that the tailing part of the resist pattern recedes irregularly at an etching process. Thus, the dimension of the capacity storage electrode contact 11 is unstable.
The above mentioned disadvantages may increase contact resistance and cause connection defect with a decreased area of the capacity storage electrode contact 11.
The present invention has its object of preventing the contact defect due to mask displacement and tailing of the resist pattern at the photo-lithography process.